These “SoC” papers below (not GT friends, not my point here) – http://hasler.ece.gatech.edu/Published_papers/FPAA_Papers/index.html – emphasize the possibility of very low power, compact neuromorphic designs that include primitive analog components. This fits the kind of thing I have seen implemented on store-bought plastic trash bags. For EDA, it would be valuable to be able to take particular classes of mathematical forms or “restricted Simulink type” components & fit that into a complete description of an implementation. So research Qs:

a) What should be the class of input forms?

b) What search processes to look for suitable implementation designs?

S. George, S. Kim, S. Shah, J. Hasler, M. Collins, F. Adil, R. Wunderlich, S. Nease, and S. Ramakrishnan “A Programmable and Configurable Mixed-Mode FPAA SOC,” IEEE Transactions on VLSI, January 2016.

Programming Infrastructure used in the SoC FPAA IC. FG Programming pdf
S. Kim, J. Hasler, and S. George, “Integrated Floating-Gate Program- ming Environment for System-Level ICs,” Transactions on VLSI, January 2016.
High Level Tools
M. Collins, J. Hasler, and S. George, “An Open-Source Tool Set Enabling Analog-Digital-Software Co-Design,” Journal of Low Power Electronics and Applications, January 2016.